As discussed generally in Digital Telephony, Second Edition (John Bellamy, John Wiley & Sons, Inc.) at Chapter 7, the problems associated with network synchronization control and management include maintaining a smooth payload clock at a network node. As noted there, a number of factors are associated with the problem of variations in the clock signal as received downstream from the original sender, including clock instability, noise and interference, effective changes in the length of the transmission medium, changes in the velocity of propagation, doppler shifts, irregular timing information, etc., all of which affect the received clock downstream from the sending source. Typically, elastic stores have been used in the recovery of clock information with using phase locked loops in association with a variable control oscillator to adjust the read signal associated with the data stored in the elastic store for transmission further downstream.
In addition, since the adoption of synchronous optical network standards, such as SONET and the CCITT counterpart known as Synchronous Digital Hierarchy (SDH), standard ways for formatting digital signals, such as DS-1, DS-1C, DS-2, DS-3 and CCITT counterparts, within a synchronous payload envelope (SPE, called a virtual container --VC-- by CCITT) have existed. The SONET and the SDH standards provide for movement of the SPE within the SONET or SDH defined frame. Movement of the payload effectively means a change in the rate at which the digital signal is being written at a node of the synchronous network. Desynchronizers attempt to smooth this rate as read from the node so that the extracted digital signal has a payload clock frequency as constant as possible, thereby minimizing this rate of change, otherwise known as jitter.
As the payload is removed from the synchronous frame containing line and section overhead, the resulting periodically discontinuous payload clock signal must be smoothed to a periodically continuous clock signal associated with the resynchronized payload output data. An elastic store provides straightforward means for accomplishing this result. The payload data as removed from the synchronous frame is thus written into the elastic store at the periodically discontinuous ram. This discontinuous rate, as averaged over many synchronous frames, is then used to read data from the elastic store at the digital signal's periodically continuous rate. The pointer mechanism comprises a set (pointer word is actually in 2 bytes) of information which is used to define the start of the next SONET synchronous payload envelope (SPE) in order to allow the envelope to move within the SONET frame. When there is a pointer adjustment, the amount of data within the SPE for the current SONET frame changes by one byte. However, it is not desirable to make an instantaneous adjustment in the elastic store read clock to reflect this change. Rather, it is desirous that the read clock rate gradually increase or decrease to accommodate the pointer adjustment so as to minimize output jitter and to bring the read clock frequency back to average write clock frequency. The slower the adjustment is made to the read clock frequency, the less output jitter (rate of change of the read clock) is generated.
Ideally if the payload (digital signal) did not move within the synchronous frame and if asynchronous stuff bits were not required within the payload itself, no jitter would be seen on the elastic store read clock. However, both payload movement within the synchronous frame, known as pointer movement, and asynchronous stuff bits to accommodate data rate fluctuation within the payload itself, do occur.
A listing of prior art documents which are directed to the problems associated with desynchronizers, including SONET desynchronizers is presented in Table 1.
TABLE 1 ______________________________________ REFERENCES ______________________________________ 1. T1.105-1991 "Digital Hierarchy - Optical Interface Rates and Formats Specification (SONET), Section 7 Synchronization 2. T1X1.6/88-028 "Analysis of Jitter & Wander Associated with Pointer Adjustments," British Telecom. (2a) T1X1.6/88-029 "A Possible Design for a Desynchronizer Accommodating Pointer Adjustments," British Telecom. 3. T1X1.6/89-029 "Results of Simulations of a Possible Desynchronizer Design," British Telecom. 4. T1X1.6/88-026 "A Synchronous Desynchronizer." Bellcore Signals," Bellcore. 5. T1X1.6/88-041 "Pointer Spreading Desynchronizer," Northern Telecom. (5a) T1X1.3/92-071 "Jitter Accumulation Results in SONET Islands for Milli-Hertz NE Clock Bandwidths," Alcatel. (5b) T1X1.3/92-072 "DS3 Payload Output Jitter Proposal," Alcatel. (5c) T1X1.3/92-017 "Additional SONET Islands Jitter Simulation Results," Alcatel. (5d) T1X1.3/92-006 "Initial Draft of SONET Jitter Standard," Tellabs. 6. "Short Term Stability Specification of SONET Timing Reference Signals," Bellcore. 7. T1 LB280 "A Technical Report on the Effects of SONET on Payload Output Jitter, T1X1.3 8. T1X1.6/90-005 "STS-1 and OC-N Jitter Proposal," Alcatel 9 "Design and Performance Verification of a SONET-TO-DS3 Desynchronizer", Hamlin, Jr., TranSwitch Corp., Shelton, Connecticut, published before February 25, 1992. 10. U.S. Pat. No. 4,996,698 - Nelson - February 26, 1991 11. U.S. Pat. No. 5,052,025 - Duff et al - September 24, 1991 ______________________________________
The problem addressed in prior art devices is thus to smooth the receive clock of the digital signals contained within the SPE, such as a DS-3 signal or a DS-1 signal so as to minimize output jitter while simultaneously inhibiting elastic store overflow or underflow.
Prior art techniques associated with SONET to DS-3 desynchronizers typically cause output phase transitions in the one unit interval (UI) range (one bit), which at the DS-3 rate corresponds to 22 nanoseconds (ns) (1/44.736 mb/sec). Such large phase steps can cause high levels of jitter on the recovered clock since they are only filtered with relatively high bandwidth phase lock loops (PLL's). Various manufacturers have devices which cause such levels of jitter, as noted in Table 1.
In the technique disclosed in U.S. Pat. No. 4,996,698, the pointer changes are smoothed using a high-pass filter and summing the output of this filter with the periodically discontinuous payload clock and then applying this summed signal to a type 2 low-pass filter using a phase locked loop synchronizing technique.
U.S. Pat. No. 5,052,025 discloses an adaptive bit leaking arrangement in conjunction with a digital phase locked loop and synchronizing elastic store to achieve improved jitter performance. An estimate of a bit leaking interval is adaptively obtained based on the intervals between a sequence of consecutive pointer adjustments in the received signal.
Although these prior art techniques have been able to reduce output jitter associated with pointer adjustments, recent SONET/asynchronous jitter studies such as the Alcatel T1X1.3 contributions to T1X 1.3/92-017, -041 have shown that peak jitter levels of 0.2 -0.25 (UI) unit interval per pointer, or lower are required to limit pointer generated jitter to reasonable allocation levels. At the present time it has been found that the filtering algorithm used in a DS-1 rate desynchronizer as disclosed in applicant's copending application Ser. No. 771,037, is not readily adaptable to a DS-3 rate. This is due to the fact that a high frequency over sampling clock must be used which is not practicable at the present time for a DS-3 rate. The present invention overcomes such problems associated with the prior art while providing improved fault recovery and programmability of the desynchronizer parameters. It also uses an iterative calculation engine which is able to calculate the bit leaking value on a repetitive basis while dramatically reducing the number of gates necessary to implement the circuitry as an ASIC.